Material property, compatibility, and reliability issues in diamond-enhanced, GaAs-based plastic packages

GaAs MESFET (chip&wire and flip-chip) and PHEMT devices were plastic-packaged using CVD diamond (CVDD) in SOIC and QFP geometries, respectively. The compatibility of CVDD insertion was considered with respect to thermal, thermo-mechanical, and chemical properties as well as spatial arrangement and dimensional extent of the materials comprising the package structure. Predictive finite element modeling showed optimum thermal and thermo-mechanical designs (minimum thermal resistance, R th, for the dominant thermal path; minimum principal stress, S1, in the GaAs) to consist of (1), a leadframe-substrate (CVDD) ‘overlap’ configuration, (2), an all-metallic assembly process (die attach + leadframe attach) and (3), a ‘compliant’ metal interlayer between GaAs and CVDD. Additionally, oxidative chemical treatment of the CVDD surface provided a strong affinity between the polymer encapsulant and CVDD, resisting over 50 cycles of 15 min boiling water immersion and peel-adhesion tests before exceeding the criterion for failure. Employing these considerations in the fabrication of CVDD-enhanced GaAs plastic packages provided for significant improvements over the conventional package design with a Cu leadframe substrate. The GaAs/CVDD plastic package performance milestones were: (a) greater than 50% reductions in Θj relative to the Cu die-paddle package ( Θj chip&wire = 127°C and Θj flip-chip = 141°C for 2.5 W, 1 GHz, GaAs MESFET; (b) 20 W continuous operation for 96 h with Θj chip&wire = 140°C for a 30 W, 3–6 GHz, GaAs PHEMT; (c) passed MIL STD 883 1000 cycle, −55 to 125°C temperature exposure; (d) passed highly accelerated stress testing, HAST, (110°C, 200 h, 85% RH, 3.1 atm). Electrical performance testing ( S-parameter) on metallized CVDD coplanar transmission lines and diamond-enhanced, coplanar GaAs flip-chip MESFET packages showed: (a), transmission line performance equivalent to Al 2O 3 (