Mapping and scheduling for heterogeneous architectures

Extensive and computationally complex signal processing and control applications are commonly constructed from small computational blocks where the load decomposition and balance may not be easily achieved. This requires the development of mapping and scheduling strategies based on application to processor matching. In this context several application algorithms are utilised and investigated in this work within the development framework (DF) approach. The DF approach supports the specification, design and implementation of real-time control systems. It also contains several mapping and scheduling tools to improve the performance of systems as well as tools for code generation. To improve the performance of an application, a new approach, namely the priority-based genetic algorithm (PBGA), is developed and reported in this article. The approach is applied to several applications using parallel and distributed heterogeneous architectures and its performance verified in comparison to several previously developed strategies.