Simulation of Enhanced Interface Trapping Due to Carrier Dynamics in Warped Valence Bands in SiGe Devices

Simulation of Enhanced Interface Trapping Due to Carrier Dynamics in Warped Valence Bands in SiGe Devices

Much of the potential of SiGe for p-MOSFET application is reduced by the lower than expected hole mobilities which are likely to be lowered by interface roughness scattering. The present paper analyses a hitherto unrecognised enhancement of interface scattering and trapping process which arises from...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:VLSI Design 2001-01, Vol.2001 (1-4), p.453-458
Hauptverfasser: Barker, J R, Watling, J R
Format: Artikel
Sprache:eng
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Much of the potential of SiGe for p-MOSFET application is reduced by the lower than expected hole mobilities which are likely to be lowered by interface roughness scattering. The present paper analyses a hitherto unrecognised enhancement of interface scattering and trapping process which arises from the complex hole dynamics in the warped heavy hole band.
ISSN:1065-514X
DOI:10.1155/2001/70818