Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's
The potential impact of high- Kappa gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined...
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| Veröffentlicht in: | IEEE transactions on electron devices 1999-01, Vol.46 (1), p.261-262 |
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| container_title | IEEE transactions on electron devices |
| container_volume | 46 |
| creator | Cheng, B. Cao, M. Vande Voorde, P. Greene, W. Stork, H. Yu, Z. Woo, J.C.S. |
| description | The potential impact of high- Kappa gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined by the gate thickness-to-length aspect ratio. In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation |
| doi_str_mv | 10.1109/16.737469 |
| format | Article |
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It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined by the gate thickness-to-length aspect ratio. In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation</description><identifier>ISSN: 0018-9383</identifier><identifier>DOI: 10.1109/16.737469</identifier><language>eng</language><subject>Devices ; Dielectric constant ; Dielectrics ; Drains ; Gates ; Performance degradation ; Permittivity ; Stacks</subject><ispartof>IEEE transactions on electron devices, 1999-01, Vol.46 (1), p.261-262</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c223t-e994e868a25f999419d11c0d1158e6ca5ba0e27a42ec193cc2eba7b5988ece3b3</citedby><cites>FETCH-LOGICAL-c223t-e994e868a25f999419d11c0d1158e6ca5ba0e27a42ec193cc2eba7b5988ece3b3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27901,27902</link.rule.ids></links><search><creatorcontrib>Cheng, B.</creatorcontrib><creatorcontrib>Cao, M.</creatorcontrib><creatorcontrib>Vande Voorde, P.</creatorcontrib><creatorcontrib>Greene, W.</creatorcontrib><creatorcontrib>Stork, H.</creatorcontrib><creatorcontrib>Yu, Z.</creatorcontrib><creatorcontrib>Woo, J.C.S.</creatorcontrib><title>Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's</title><title>IEEE transactions on electron devices</title><description>The potential impact of high- Kappa gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. 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In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation</description><subject>Devices</subject><subject>Dielectric constant</subject><subject>Dielectrics</subject><subject>Drains</subject><subject>Gates</subject><subject>Performance degradation</subject><subject>Permittivity</subject><subject>Stacks</subject><issn>0018-9383</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1999</creationdate><recordtype>article</recordtype><recordid>eNp9kMtOwzAQRb0AiVJY8Ade8Vi4-JE49hKV8lJRF8A6cpxJapQ2xZMu-DXEN_SbMCprNnPvjI7mSpeQM8EnQnB7LfSkUEWm7QEZcS4Ms8qoI3KM-J5WnWVyRJ5uAUO7pr5fY6ghuiEkR_uGLkO7ZLsv2roBaB2gAz_E4JE2faS4rVhKYbvvFX1evNzNXi_whBw2rkM4_dMxeUv36QObL-4fpzdz5qVUAwNrMzDaOJk3NnlhayE8TyM3oL3LK8dBFi6T4IVV3kuoXFHl1hjwoCo1Juf7v5vYf2wBh3IV0EPXuTX0WyyltjK3XCXw8l9Q6EIoYbJCJ_Rqj_rYI0Zoyk0MKxc_S8HL3zITXO7LVD_CNGgY</recordid><startdate>19990101</startdate><enddate>19990101</enddate><creator>Cheng, B.</creator><creator>Cao, M.</creator><creator>Vande Voorde, P.</creator><creator>Greene, W.</creator><creator>Stork, H.</creator><creator>Yu, Z.</creator><creator>Woo, J.C.S.</creator><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>KR7</scope><scope>L7M</scope><scope>7U5</scope></search><sort><creationdate>19990101</creationdate><title>Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's</title><author>Cheng, B. ; Cao, M. ; Vande Voorde, P. ; Greene, W. ; Stork, H. ; Yu, Z. ; Woo, J.C.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c223t-e994e868a25f999419d11c0d1158e6ca5ba0e27a42ec193cc2eba7b5988ece3b3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Devices</topic><topic>Dielectric constant</topic><topic>Dielectrics</topic><topic>Drains</topic><topic>Gates</topic><topic>Performance degradation</topic><topic>Permittivity</topic><topic>Stacks</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Cheng, B.</creatorcontrib><creatorcontrib>Cao, M.</creatorcontrib><creatorcontrib>Vande Voorde, P.</creatorcontrib><creatorcontrib>Greene, W.</creatorcontrib><creatorcontrib>Stork, H.</creatorcontrib><creatorcontrib>Yu, Z.</creatorcontrib><creatorcontrib>Woo, J.C.S.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Cheng, B.</au><au>Cao, M.</au><au>Vande Voorde, P.</au><au>Greene, W.</au><au>Stork, H.</au><au>Yu, Z.</au><au>Woo, J.C.S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's</atitle><jtitle>IEEE transactions on electron devices</jtitle><date>1999-01-01</date><risdate>1999</risdate><volume>46</volume><issue>1</issue><spage>261</spage><epage>262</epage><pages>261-262</pages><issn>0018-9383</issn><abstract>The potential impact of high- Kappa gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. 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| fulltext | fulltext |
| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 1999-01, Vol.46 (1), p.261-262 |
| issn | 0018-9383 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_26925903 |
| source | IEEE Electronic Library (IEL) |
| subjects | Devices Dielectric constant Dielectrics Drains Gates Performance degradation Permittivity Stacks |
| title | Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's |
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