Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's

Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's

The potential impact of high- Kappa gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined...

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Veröffentlicht in:IEEE transactions on electron devices 1999-01, Vol.46 (1), p.261-262
Hauptverfasser: Cheng, B., Cao, M., Vande Voorde, P., Greene, W., Stork, H., Yu, Z., Woo, J.C.S.
Format: Artikel
Sprache:eng
Schlagworte:
Devices
Dielectric constant
Dielectrics
Drains
Gates
Performance degradation
Permittivity
Stacks
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Zusammenfassung:The potential impact of high- Kappa gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined by the gate thickness-to-length aspect ratio. In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation
ISSN:0018-9383
DOI:10.1109/16.737469