Developing a 0.18-micron CMOS process

Developing a 0.18-micron CMOS process

The authors discuss ways to develop certain modules that are required to generate a new generation of devices and meet targeted goals. They also introduce the integration of low-k material to improve IMD parasitic capacitance.

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE MICRO 1999-09, Vol.19 (5), p.16-22
Hauptverfasser: Haond, M., Basso, M.-T., deCoster, E., Guelen, J., Lair, C.
Format: Artikel
Sprache:eng
Schlagworte:
Capacitance
CMOS
CMOS integrated circuits
CMOS process
CMOS technology
Devices
Electrical engineering
Implants
Manufacturing industries
Manufacturing processes
Modules
MOS devices
Parasitic capacitance
R&D
Research & development
Threshold voltage
Transistors
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The authors discuss ways to develop certain modules that are required to generate a new generation of devices and meet targeted goals. They also introduce the integration of low-k material to improve IMD parasitic capacitance.
ISSN:0272-1732
1937-4143
DOI:10.1109/40.798105