Performance analysis of speeded‐up high‐speed packet switches

In this paper, we study the performance of high‐speed packet switches, where the switch fabric operates at a slightly higher speed than the links, i.e., a speeded‐up switch. Such structures are by no means new and there are two well studied architectures in the literature for such packet switches: pure input queueing (no speedup) and pure output queueing (speedup of N, the number of links), with output queueing switches offering substantial performance benefits. However, as link speeds keep increasing, the speedup of N needed for pure output queueing becomes a significant technical challenge. This is one of the main reasons for the renewed interest in moderately speeded‐up switch fabrics. The aim of this paper is to highlight the result that only a moderate speed‐up factor (less than two) is sufficient to achieve full input link utilization. In particular, we emphasize that this holds, even without relying on a central switch controller making intelligent decisions on which packets to schedule through the switch. As shown in recent works, i.e., [5, 17, 20, 23, 25] there are clearly benefits to using intelligent controllers, but they do come at a cost. Instead, in this paper we focus on what can be achieved by relying simply on switch speedup. We do so by means of analysis and simulations. Our analysis provides explicit expressions for the average queue length in switches with integer and rational speedups. The results are complemented by simulations that are used to obtain delay estimates, and which also allow us to extend our investigation to shared memory switches for which we find that good performance can be achieved with an even lower speedup.