A process simplification scheme for fabricating self-aligned silicided trench-gate power MOSFETs

A practical process scheme that fabricates self-aligned silicided trench-gate power MOSFETs has been proposed to increase the packing density and simplify the process of trench-gate power MOSFETs, by saving the two masking steps for trench gate and source regions. A device with a specific on-state resistance of about 1.5 Ω cm and a blocking voltage larger than 30 V can be obtained by simply using the self-aligned silicided trench-gate scheme. Hence, with reducing the cell pitch size to be below 2 μm, the process scheme should be promising and practical for achieving a specific on-resistance smaller than 0.2 mΩ cm 2 and a blocking voltage higher than 30 V.