Validation of an architectural level power analysis technique

This paper presents a technique used to do power analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP and a 32-bit RISC on a single chip. Our power estimator provides power consumption data of the architecture based on the instruction/data flow stream. We demonstrate the accuracy of the estimator by comparing the power values it produces against measurements made by a gate level power simulator for the same benchmark set. Our estimation approach has been shown to provide very efficient, accurate power analysis at the architectural level.