Testing the 500-MHz IBM S/390 microprocessor

The design-for-test framework of the 500-MHz CMOS central processor uses specific tests to ensure the highest reliability of components within a system. Some of the same test patterns are applied in chip manufacturing and system-level tests.

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Bibliographische Detailangaben
Veröffentlicht in:	IEEE design & test of computers 1998-07, Vol.15 (3), p.83-89
Hauptverfasser:	Foote, T.G., Hoffman, D.E., Huott, W.V., Koprowski, T.J., Kusko, M.P., Robbins, B.J.
Format:	Artikel
Sprache:	eng
Schlagworte:	Automatic testing Built-in self-test Clocks Logic arrays Logic testing Microprocessors Programmable logic arrays Random access memory Registers System testing
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Beschreibung
Zusammenfassung:	The design-for-test framework of the 500-MHz CMOS central processor uses specific tests to ensure the highest reliability of components within a system. Some of the same test patterns are applied in chip manufacturing and system-level tests.
ISSN:	0740-7475 1558-1918
DOI:	10.1109/54.706038