Simulating the impact of pattern-dependent poly-CD variation on circuit performance

In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 /spl mu/m 64/spl times/8 SRAM macrocell layout. For this example, the impact as measured thr...

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Veröffentlicht in:	IEEE transactions on semiconductor manufacturing 1998-11, Vol.11 (4), p.552-556
Hauptverfasser:	Stine, B.E., Boning, D.S., Chung, J.E., Ciplickas, D.J., Kibarian, J.K.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuit optimization Circuit simulation Design methodology Electronics Exact sciences and technology Gaussian distribution Laboratories Macrocell networks Microelectronic fabrication (materials and surfaces technology) Monte Carlo methods MOS devices Random access memory Semiconductor device measurement Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Beschreibung
Zusammenfassung:	In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 /spl mu/m 64/spl times/8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell.
ISSN:	0894-6507 1558-2345
DOI:	10.1109/66.728551