Model for metal interconnection design rule optimization

Joule heating for short time pulses causing internal breakdown of metal interconnects in ESD/EOS protection circuits and I/O buffers has been analyzed. A model has been developed for the optimization of design rules by incorporating maximum allowable current density, the geometry and type of metal lines, surrounding oxide layer and pulse width The model shows good agreement with the experimental results and can be used to generate robust interconnection design guidelines for ESD/EOS and I/O buffers.