HW/SW co-simulation for fast design-space exploration of multiprocessor embedded systems

A crucial problem in designing multiprocessor embedded systems is the possibility of efficiently comparing the timing behaviour of different system configurations to select, during the early stages of the design process, a suitable trade-off between performance and cost. The goal of the paper is to present a timing system-level simulation strategy allowing the user to simulate, in a flexible and effective manner, a multiprocessor embedded architecture such that the impact of modifying the main configuration issues of the overall system can be evaluated. The relevant aspects a user can inspect to explore the design space concern the communication architecture, the process-scheduling policy and the type of the processing elements. The value added by the proposed simulation strategy is the possibility of validating the behaviour of the overall systems while exploring the design space, considering aspects of both hardware/software and software/software partitioning. The methodology has been implemented and it currently supports the partitioning step in an existing hardware/software co-design environment.