Process technology and integration challenges for high performance interconnects

Interconnect metallization for 0.18 μm technology presents many new challenges for the process technologies. The DRAM device architecture imposes severe requirements of shallow junctions and narrow line widths, which combine to put constraints on the thermal budget while requiring low RC time constant for the interconnects. A number of new materials, such as TiSi x , TiN, W, WN, Pt, and Ru are under consideration for interconnect and capacitor plate metallization. These materials need to provide low resistance lines, be thermally stable, and have no deleterious effects on the gate oxide and capacitor dielectric, and they must be compatible with the overall process flow. Deposition processes for interconnect materials as well as interlevel dielectrics with superior conformality are necessary for a complete fill without voids. A review of the requirements for a manufacturable interconnect scheme and the limitations of the current technology is presented.