The intelligent approach to register-transfer level synthesis

This paper describes a VHDL high-level synthesis system HLS/BIT with the emphasis on its register-transfer level (RTL) binding and technology mapping subsystem that adopts an intelligent technique to build the intelligent binding component library (IBCL). The component instantiated mechanism and the...

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Veröffentlicht in:Artificial intelligence in engineering 1998-07, Vol.12 (3), p.143-147
Hauptverfasser: Zongfu, Yan, Mingye, Liu, Hantao, Song
Format: Artikel
Sprache:eng
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Zusammenfassung:This paper describes a VHDL high-level synthesis system HLS/BIT with the emphasis on its register-transfer level (RTL) binding and technology mapping subsystem that adopts an intelligent technique to build the intelligent binding component library (IBCL). The component instantiated mechanism and the knowledge-based approach to RTL technology mapping are also presented.
ISSN:0954-1810
DOI:10.1016/S0954-1810(96)00027-1