Accurate and efficient macromodel of submicron digital standard cells
In this paper a new analytic gate delay modelingtechnique is presented that allows to accuratelyreproduce the timing behavior of deep submicron digitalstandard cells for a large range of operating conditions.The proposed technique sensibly improves the accuracyof the existing analytic delay models a...
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| creator | Forzan, Cristiano Franzini, Bruno Guardiani, Carlo |
| description | In this paper a new analytic gate delay modelingtechnique is presented that allows to accuratelyreproduce the timing behavior of deep submicron digitalstandard cells for a large range of operating conditions.The proposed technique sensibly improves the accuracyof the existing analytic delay models and it usuallyrequires less simulations for the cell characterization.Moreover it is compatible with the most advanced interconnectdelay models that have been recently proposed inthe literature. |
| doi_str_mv | 10.1145/266021.266305 |
| format | Conference Proceeding |
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Franzini, Bruno ; Guardiani, Carlo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a254t-529cc3862adb8c1b69d0f2af52cdd8e451f5120ed148f71d22e5550a427ca5613</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Computer systems organization -- Dependable and fault-tolerant systems and networks</topic><topic>General and reference -- Cross-computing tools and techniques -- Performance</topic><topic>Hardware -- Hardware validation -- Functional verification -- Simulation and emulation</topic><topic>Hardware -- Integrated circuits -- Semiconductor memory</topic><topic>Networks -- Network performance evaluation</topic><toplevel>online_resources</toplevel><creatorcontrib>Forzan, Cristiano</creatorcontrib><creatorcontrib>Franzini, Bruno</creatorcontrib><creatorcontrib>Guardiani, Carlo</creatorcontrib><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Forzan, Cristiano</au><au>Franzini, Bruno</au><au>Guardiani, Carlo</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Accurate and efficient macromodel of submicron digital standard cells</atitle><btitle>DAC 97: 34th Annual ACM-IEEE Design Automation Conference</btitle><date>1997-01-01</date><risdate>1997</risdate><spage>633</spage><epage>637</epage><pages>633-637</pages><issn>0738-100X</issn><isbn>0897919203</isbn><isbn>9780897919203</isbn><abstract>In this paper a new analytic gate delay modelingtechnique is presented that allows to accuratelyreproduce the timing behavior of deep submicron digitalstandard cells for a large range of operating conditions.The proposed technique sensibly improves the accuracyof the existing analytic delay models and it usuallyrequires less simulations for the cell characterization.Moreover it is compatible with the most advanced interconnectdelay models that have been recently proposed inthe literature.</abstract><cop>New York, NY, USA</cop><pub>ACM</pub><doi>10.1145/266021.266305</doi><tpages>5</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0738-100X |
| ispartof | DAC 97: 34th Annual ACM-IEEE Design Automation Conference, 1997, p.633-637 |
| issn | 0738-100X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_26472886 |
| source | IEEE Electronic Library (IEL) |
| subjects | Computer systems organization -- Dependable and fault-tolerant systems and networks General and reference -- Cross-computing tools and techniques -- Performance Hardware -- Hardware validation -- Functional verification -- Simulation and emulation Hardware -- Integrated circuits -- Semiconductor memory Networks -- Network performance evaluation |
| title | Accurate and efficient macromodel of submicron digital standard cells |
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