Area-efficient multipliers for digital signal processing applications

An area-efficient parallel sign-magnitude multiplier that receives two N-bit numbers and produces an N-bit product, referred to as a truncated multiplier, is described. The quantization of the product to N bits is achieved by omitting about half the adder cells needed to add the partial products but...

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Veröffentlicht in:	IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 1996-02, Vol.43 (2), p.90-95
Hauptverfasser:	Kidambi, S.S., El-Guibaly, F., Antoniou, A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Adders Applied sciences Digital filters Digital signal processing Digital signal processing chips Electronics Estimation error Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Quantization Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Senior members Signal processing algorithms Signal to noise ratio
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