Circuit delay calculation considering data dependent delays

Accurate detection of both maximun and minimum circuit delay times and the detection of input vectors that produce those delays are crucial tasks in the design and testing of high speed CMOS circuits. This is especially true for timing disciplines, such as single phase latching, wave pipelining, and asynchronous design, where combinational logic delays paths are designed to be nearly equal and timing constraints are very tight. For these design methodologies, traditional timing analysis based on gate delay models assuming single delay values forgates or delay values based only on gate inputs is not sufficient. For example, two input CMOS NAND gate delay can vary by as much as a factor of two based on whether one input is changing or both inputs are changing. This implies that, for accurate detection of maximum and minimum overall delay, sensitization of multiple paths must be considered to ascertain feasibility of multiple simulationeous input transitions at particular gates. This paper considers this problem beginning with a brief discussion of CMOS gate delays. An algorithm is then presented that accurately detects both maximum and minimum delays considering the effect of delay differences due to rising and falling transitions and due to single vs. multiple simultaneous signal changes at gate inputs. Results of this process are demonstrated in a prototype timing analyzer XTV.