VLSI architecture for polygon recognition

The recognition of polygons in 3-D space is an important task in robot vision. Advances in VLSI technology have now made it possible to implement inexpensive, efficient, and very fast custom designs. In this paper, a class of VLSI architectures are proposed for this computationally intensive task, which makes use of a set of local shape descriptors for polygons that are invariant under affine transformations, i.e., translation, scaling, rotation, and orthographic projection from 3-D to any 2-D plane. The recognition procedure is based on the matching of edge length ratios using a simplified version of the dynamic programming procedure commonly employed for string matching. The matching procedure also copes with partial occlusion of polygons. The architectures are systolic and fully utilize the principles of pipelining and parallelism in order to obtain high speed and throughput. A prototype VLSI chip implementing one of the proposed architectures is currently being built at the University of South Florida.