Self-learning digital neural network using water-scale LSI

For high-speed learning by a large artificial neural network, we propose a dual-network architecture using wafer-scale integration (WSI) technology. By using 0.8- mu m CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5-in silicon wafers. Neural functions and...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1993-01, Vol.28 (2), p.106-114
Hauptverfasser:	Yasunaga, Moritoshi, Masuda, Noboru, Yagyu, Masayoshi, Asai, Mitsuo, Shibata, Katsunari, Ooyama, Mitsuo, Yamada, Minoru, Sakaguchi, Takahiro, Hashimoto, Masashi
Format:	Artikel
Sprache:	eng
Online-Zugang:	Volltext
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