Self-learning digital neural network using water-scale LSI

For high-speed learning by a large artificial neural network, we propose a dual-network architecture using wafer-scale integration (WSI) technology. By using 0.8- mu m CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5-in silicon wafers. Neural functions and the back propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30-cm cube. Dual-network architecture allowed high-speed learning at more than 2 giga-connections updated per second (GCUPS). The high fault tolerance of the neural network and the proposed defect-handling techniques overcame the yield problem of WSI. This hardware has a self-organization capability for eliminating defective neurons by itself. EXCLUSIVE-OR's output patterns for input patterns could be learned even when there were defective neurons in the hidden layer of the network. This hardware can be connected to a host workstation and used for simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware. The system could learn one signature or one stock price characteristics pattern in 3 to 10 s, which is 1 to 3 times as fast as BP simulation on a Hitachi S-820 supercomputer.