Modelling and improving the on-resistance of LDMOS RESURF devices

We present in this paper some techniques to decrease the value of the drift region on-resistance of a lateral DMOS transistor (LDMOS). We first evaluate the technique using a shallow implanted layer between the channel and the drain of the transistor, whose doping is somewhat higher than the background doping level. Dose and energy should be carefully calibrated in order to ensure the largest on-resistance improvement but a good trade-off with the breakdown voltage is difficult. Secondly, we assess the on-resistance improvement achievable using a semi-resistive layer deposited between the gate and drain metals above the oxide layer. This will enhance the accumulated drift area and consequently decrease the on-resistance. The achievable improvement is less than for the surface doping technique. We propose to use both techniques to obtain the best on-resistance improvement/breakdown voltage trade-off. Surface doping will be employed to decrease the on-resistance and the semi-resistive layer will keep the breakdown voltage to its optimal value. We assess and demonstrate, with both analytical and numerical analyses, that large improvements can be achieved with these techniques without degrading the voltage handling capacity of the device. The on-resistance can be lowered by 40 to 66%. Experimental LDMOS transistors will be presented which exhibit good agreement with the theoretical predictions.