Reduction of linewidth variation for the gate conductor level by lithography based on a new antireflective layer

An antireflective bilayer consisting of a-Sin on top of a-Si has been developed in particular for the application over gate level topography with a TEOS/polySi substrate stack furnishing high substrate reflectivity, especially in case of i-line exposure. The increase in complexity of the optimized overall-process seems acceptable in view of the distinctly reduced CD variations obtained with 16M g- and i-line lots when compared to the standard technique using dyed resist.