Electrical measurement of silicon film and oxide thicknesses in partially depleted SOI technologies

This paper discusses the electrical measurement of silicon film, gate oxide and buried oxide thicknesses in partially depleted SOI CMOS technologies. For the first time a technique is presented that allows extraction of all three thicknesses, as well as the average silicon film doping concentration, using static threshold voltage measurements only. All measurements and extraction procedures can easily be fully automated, making this method suitable for both accurate parameter extraction and process control. The results obtained with this new technique have been verified by SEM cross-section measurement and a comparison is made with other electrical techniques.