Harvest rate of reconfigurable pipelines
For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. The authors give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: there are n pipeline...
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| Veröffentlicht in: | IEEE transactions on computers 1996-10, Vol.45 (10), p.1200-1203 |
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| container_title | IEEE transactions on computers |
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| creator | Weiping Shi Ming-Feng Chang Fuchs, W.K. |
| description | For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. The authors give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: there are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the "shifting" reconfiguration as weighted chains in a partial ordered set, they prove when n=/spl theta/(m), the harvest rate is between 34% and 72%. |
| doi_str_mv | 10.1109/12.543713 |
| format | Article |
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Graph</subject><subject>Parallel architectures</subject><subject>Pipelines</subject><subject>Reconfigurable architectures</subject><subject>Shape</subject><subject>Software</subject><subject>Supercomputers</subject><subject>Theoretical computing</subject><subject>Topology</subject><subject>Very large scale integration</subject><subject>Wires</subject><issn>0018-9340</issn><issn>1557-9956</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1996</creationdate><recordtype>article</recordtype><recordid>eNqF0D1LA0EQBuBFFIzRwtbqChEtLs7s1-2WEtQIARutl81mVk4ud-duIvjvPbmQ1mqKeeZleBm7RJghgr1HPlNSVCiO2ASVqkprlT5mEwA0pRUSTtlZzp8AoDnYCbtd-PRNeVskv6Wii0Wi0LWx_tglv2qo6OuemrqlfM5Oom8yXeznlL0_Pb7NF-Xy9fll_rAsA7fVtkQwRq2CkGsJVEUDGEiaCHEtovago1oh50Z74WWIJkgEYUjbtQxaaghiym7G3D51X7vhM7epc6Cm8S11u-y4EVxa4P9DjVpxBQO8G2FIXc6JoutTvfHpxyG4v9IccjeWNtjrfajPwTcx-TbU-XDApZHK6IFdjawmosN2n_ELeMRxrA</recordid><startdate>19961001</startdate><enddate>19961001</enddate><creator>Weiping Shi</creator><creator>Ming-Feng Chang</creator><creator>Fuchs, W.K.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19961001</creationdate><title>Harvest rate of reconfigurable pipelines</title><author>Weiping Shi ; Ming-Feng Chang ; Fuchs, W.K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c297t-10885bc34d40e7f801ce48f0fd3f6a06f5b12286a3a4cf8c41038e69d4c6460c3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Applied sciences</topic><topic>Computer science</topic><topic>Computer science; control theory; systems</topic><topic>Computer systems and distributed systems. User interface</topic><topic>Equations</topic><topic>Exact sciences and technology</topic><topic>Information retrieval. Graph</topic><topic>Parallel architectures</topic><topic>Pipelines</topic><topic>Reconfigurable architectures</topic><topic>Shape</topic><topic>Software</topic><topic>Supercomputers</topic><topic>Theoretical computing</topic><topic>Topology</topic><topic>Very large scale integration</topic><topic>Wires</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Weiping Shi</creatorcontrib><creatorcontrib>Ming-Feng Chang</creatorcontrib><creatorcontrib>Fuchs, W.K.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Weiping Shi</au><au>Ming-Feng Chang</au><au>Fuchs, W.K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Harvest rate of reconfigurable pipelines</atitle><jtitle>IEEE transactions on computers</jtitle><stitle>TC</stitle><date>1996-10-01</date><risdate>1996</risdate><volume>45</volume><issue>10</issue><spage>1200</spage><epage>1203</epage><pages>1200-1203</pages><issn>0018-9340</issn><eissn>1557-9956</eissn><coden>ITCOB4</coden><abstract>For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. 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| ispartof | IEEE transactions on computers, 1996-10, Vol.45 (10), p.1200-1203 |
| issn | 0018-9340 1557-9956 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Computer science Computer science control theory systems Computer systems and distributed systems. User interface Equations Exact sciences and technology Information retrieval. Graph Parallel architectures Pipelines Reconfigurable architectures Shape Software Supercomputers Theoretical computing Topology Very large scale integration Wires |
| title | Harvest rate of reconfigurable pipelines |
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