Harvest rate of reconfigurable pipelines
For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. The authors give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: there are n pipeline...
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Veröffentlicht in: | IEEE transactions on computers 1996-10, Vol.45 (10), p.1200-1203 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. The authors give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: there are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the "shifting" reconfiguration as weighted chains in a partial ordered set, they prove when n=/spl theta/(m), the harvest rate is between 34% and 72%. |
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ISSN: | 0018-9340 1557-9956 |
DOI: | 10.1109/12.543713 |