Development of a fault model and test algorithms for embedded DRAMs

Development of a fault model and test algorithms for embedded DRAMs

Embedded DRAMs are an integral part of modern ICs. Owing to limited accessibility, the testing of embedded memories is a time consuming exercise. Such memories designed in a standard VLSI process show susceptibility to catastrophic as well as non-catastrophic defects. Taking into account catastrophi...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Sachdev, M., Verstraelen, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit faults
Circuit testing
Laboratories
Logic testing
Manufacturing
Modems
Random access memory
Read-write memory
System testing
Very large scale integration
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Beschreibung
Zusammenfassung:Embedded DRAMs are an integral part of modern ICs. Owing to limited accessibility, the testing of embedded memories is a time consuming exercise. Such memories designed in a standard VLSI process show susceptibility to catastrophic as well as non-catastrophic defects. Taking into account catastrophic and non-catastrophic defects, an accurate and efficient fault model has been developed. Using this fault model linear test algorithms of complexity 8N and 9N have been developed.< >
DOI:10.1109/TEST.1993.470620