New signal processing technique for d identical with 1 channel codes

This paper presents a strategy for reducing nonlinearities at high-recording densities; a new additional encoding scheme for DC-free d identical with 1 channel codes, and a partial response (1+D) system with 2-bit decoding. This encoding scheme, which is applicable to DC-free codes, reduces by one bit the maximum transition interval of d identical with 1 codes, and ensures a wide margin of timing offset. In order to use erasures for the error correction code, the 2-bit decoding scheme is employed in-parallel to detect errors in the decoding procedure. An improvement in the error rate by using parallel decoding is shown.