Scaling shared-bus multi-processors with multiple buses and shared caches: a performance study

Scaling shared-bus multi-processors with multiple buses and shared caches: a performance study

A new system called multiple interleaved buses is described and analysed. It attempts to balance performance and cost trade-offs in a snoopy cache multiprocessor environment. Simulation results show the new system performs almost as well as multiple independent buses, but with simpler and less costl...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Microprocessors and microsystems 1992-01, Vol.16 (7), p.339-350
Hauptverfasser: Bertoni, Jonathan, Baer, Jean-Loup, Wang, Wen-Hann
Format: Artikel
Sprache:eng
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 350
container_issue 7
container_start_page 339
container_title Microprocessors and microsystems
container_volume 16
creator Bertoni, Jonathan
Baer, Jean-Loup
Wang, Wen-Hann
description A new system called multiple interleaved buses is described and analysed. It attempts to balance performance and cost trade-offs in a snoopy cache multiprocessor environment. Simulation results show the new system performs almost as well as multiple independent buses, but with simpler and less costly implementation. (Original abstract-amended)
format Article
fullrecord <record><control><sourceid>proquest</sourceid><recordid>TN_cdi_proquest_miscellaneous_25864214</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>25864214</sourcerecordid><originalsourceid>FETCH-proquest_miscellaneous_258642143</originalsourceid><addsrcrecordid>eNqNjMsKwjAQRbNQsD7-YVbuCklfqFtR3OtaienURtKkZhLEv1exH-DqwOXcM2IJF4VI13kuJmxKdOecl7zKEnY-Kmm0vQG10mOdXiNBF03Qae-dQiLnCZ46tL-1NwgfBQmkrYcPKKlapA1I6NE3znfSKgQKsX7N2biRhnAxcMaW-91pe_jWHxEpXDpNCo2RFl2kS1auqiITRf63-AbydUdL</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>25864214</pqid></control><display><type>article</type><title>Scaling shared-bus multi-processors with multiple buses and shared caches: a performance study</title><source>Elsevier ScienceDirect Journals</source><creator>Bertoni, Jonathan ; Baer, Jean-Loup ; Wang, Wen-Hann</creator><creatorcontrib>Bertoni, Jonathan ; Baer, Jean-Loup ; Wang, Wen-Hann</creatorcontrib><description>A new system called multiple interleaved buses is described and analysed. It attempts to balance performance and cost trade-offs in a snoopy cache multiprocessor environment. Simulation results show the new system performs almost as well as multiple independent buses, but with simpler and less costly implementation. (Original abstract-amended)</description><identifier>ISSN: 0141-9331</identifier><language>eng</language><ispartof>Microprocessors and microsystems, 1992-01, Vol.16 (7), p.339-350</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780</link.rule.ids></links><search><creatorcontrib>Bertoni, Jonathan</creatorcontrib><creatorcontrib>Baer, Jean-Loup</creatorcontrib><creatorcontrib>Wang, Wen-Hann</creatorcontrib><title>Scaling shared-bus multi-processors with multiple buses and shared caches: a performance study</title><title>Microprocessors and microsystems</title><description>A new system called multiple interleaved buses is described and analysed. It attempts to balance performance and cost trade-offs in a snoopy cache multiprocessor environment. Simulation results show the new system performs almost as well as multiple independent buses, but with simpler and less costly implementation. (Original abstract-amended)</description><issn>0141-9331</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1992</creationdate><recordtype>article</recordtype><recordid>eNqNjMsKwjAQRbNQsD7-YVbuCklfqFtR3OtaienURtKkZhLEv1exH-DqwOXcM2IJF4VI13kuJmxKdOecl7zKEnY-Kmm0vQG10mOdXiNBF03Qae-dQiLnCZ46tL-1NwgfBQmkrYcPKKlapA1I6NE3znfSKgQKsX7N2biRhnAxcMaW-91pe_jWHxEpXDpNCo2RFl2kS1auqiITRf63-AbydUdL</recordid><startdate>19920101</startdate><enddate>19920101</enddate><creator>Bertoni, Jonathan</creator><creator>Baer, Jean-Loup</creator><creator>Wang, Wen-Hann</creator><scope>8FD</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>19920101</creationdate><title>Scaling shared-bus multi-processors with multiple buses and shared caches: a performance study</title><author>Bertoni, Jonathan ; Baer, Jean-Loup ; Wang, Wen-Hann</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-proquest_miscellaneous_258642143</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1992</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Bertoni, Jonathan</creatorcontrib><creatorcontrib>Baer, Jean-Loup</creatorcontrib><creatorcontrib>Wang, Wen-Hann</creatorcontrib><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology &amp; Engineering</collection><collection>Engineering Research Database</collection><jtitle>Microprocessors and microsystems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Bertoni, Jonathan</au><au>Baer, Jean-Loup</au><au>Wang, Wen-Hann</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Scaling shared-bus multi-processors with multiple buses and shared caches: a performance study</atitle><jtitle>Microprocessors and microsystems</jtitle><date>1992-01-01</date><risdate>1992</risdate><volume>16</volume><issue>7</issue><spage>339</spage><epage>350</epage><pages>339-350</pages><issn>0141-9331</issn><abstract>A new system called multiple interleaved buses is described and analysed. It attempts to balance performance and cost trade-offs in a snoopy cache multiprocessor environment. Simulation results show the new system performs almost as well as multiple independent buses, but with simpler and less costly implementation. (Original abstract-amended)</abstract></addata></record>
fulltext fulltext
identifier ISSN: 0141-9331
ispartof Microprocessors and microsystems, 1992-01, Vol.16 (7), p.339-350
issn 0141-9331
language eng
recordid cdi_proquest_miscellaneous_25864214
source Elsevier ScienceDirect Journals
title Scaling shared-bus multi-processors with multiple buses and shared caches: a performance study
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T22%3A10%3A12IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Scaling%20shared-bus%20multi-processors%20with%20multiple%20buses%20and%20shared%20caches:%20a%20performance%20study&rft.jtitle=Microprocessors%20and%20microsystems&rft.au=Bertoni,%20Jonathan&rft.date=1992-01-01&rft.volume=16&rft.issue=7&rft.spage=339&rft.epage=350&rft.pages=339-350&rft.issn=0141-9331&rft_id=info:doi/&rft_dat=%3Cproquest%3E25864214%3C/proquest%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=25864214&rft_id=info:pmid/&rfr_iscdi=true