High-quality stacked CMOS inverter

A stacked CMOS technology with enhanced device performance and small geometries is discussed. Surface-channel mobilities were measured to be 700 cm/sup 2//V-s for bulk n-channel devices and 165 cm/sup 2//V-s for the top PMOS transistors. Excellent subthreshold slope of 100 mV/decade and leakage currents below 150-fA/ mu m channel width were measured for both device types. The low-impurity crystalline silicon film on top of the bulk devices was produced by local epitaxial overgrowth, an important alternative to recrystallized silicon films for three-dimensional CMOS circuits. The structure is planarized and requires only size masks with reduced processing time.< >