Optimal matrix multiplication on fault-tolerant VLSI arrays

Optimal matrix multiplication on fault-tolerant VLSI arrays

A fault-tolerant array for matrix multiplication that explicitly incorporates mechanisms for easy testability and reconfigurability is described. All signals in the array travel only a constant distance (independent of array size) in any clock cycle. An optimal-time algorithm, designed for multiplyi...

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Veröffentlicht in:IEEE transactions on computers 1989-02, Vol.38 (2), p.278-283
Hauptverfasser: Varman, P.J., Ramakrishnan, I.V.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithm design and analysis
Algorithmics. Computability. Computer arithmetics
Applied sciences
Clocks
Computer science
control theory
systems
Exact sciences and technology
Fault tolerance
Testing
Theoretical computing
Very large scale integration
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Zusammenfassung:A fault-tolerant array for matrix multiplication that explicitly incorporates mechanisms for easy testability and reconfigurability is described. All signals in the array travel only a constant distance (independent of array size) in any clock cycle. An optimal-time algorithm, designed for multiplying matrices, is described. The algorithm is an efficient simulation of a 2-D systolic algorithm for multiplying matrices.< >
ISSN:0018-9340
1557-9956
DOI:10.1109/12.16505