Processing techniques for refractory integrated circuits (superconducting)

Processing techniques have been developed to increase yields and uniformity in superconductor integrated circuits fabricated with refractory materials. An eight-level process was used to define a ground plane, ground plane insulator, Josephson junction base and counterelectrodes, a second insulator layer, superconductor interconnections, resistors, and gold contact pads. Every layer, except the gold, was patterned by reactive ion etching (RIE). A resistor structure was developed that included an etch stop layer. The formation of polymers, which occurs with etch gases containing carbon, was inhibited by the addition of oxygen to the plasma. RIE of insulator vias was accomplished with a mixture of NF/sub 3/ and Ar that gave good selectivity for silicon dioxide over niobium. Stress-free films of niobium, molybdenum, and silicon dioxide were obtained by adjusting the sputtering gas pressure. Molybdenum resistors, deposited as a top layer, were trimmed by RIE as a post-testing step to improve circuit performance.< >