Numerical simulation of GaAs MESFETs with a p-buffer layer on a semi-insulating substrate compensated by deep traps

A numerical analysis of GaAs MESFETs with a p-buffer layer on a semi-insulating substrate is performed in which impurity compensation by traps in the substrate is considered. It is shown that the use of a thick p-buffer layer results in a lower device current due to the formation of a steep barrier...

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Veröffentlicht in:	IEEE transactions on microwave theory and techniques 1989-09, Vol.37 (9), p.1371-1379
Hauptverfasser:	Horio, K., Fuseya, Y., Kusuki, H., Yanai, H.
Format:	Artikel
Sprache:	eng
Schlagworte:	Gallium arsenide High speed integrated circuits Impurities Insulation MESFET integrated circuits Monolithic integrated circuits Numerical simulation Parasitic capacitance Semiconductor materials Substrates
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