Design and implementation of a tester for digital and linear integrated-circuit chips

An automated scheme for testing digital, linear and hybrid ICs has been designed and implemented. In the presented design some drawbacks of previously available schemes have been removed and a few new features have been added. The notable features of this tester are its simplicity, high flexibility, low cost and powerful functional presentation. The tester is easily adapted to modern ICs and permits modification of the testing programs. The limitations of this tester are identified and listed at the end of the paper, which also throws some light on further possible developments.