Design of a high performance CMOS adder for both a high performance array and an accumulator

This paper describes the design of a high performance static adder in CMOS pass logic. The adder we present is not only the fastest CMOS adder, in comparison with other published results using the same model and process parameters, but it is also the most area efficient. An attempt to design a high performance parallel adder by exploiting the failures of the designed adder is discussed.