Competitive neural architecture for hardware solution to the assignment problem

A neural network architecture for competitive assignment is presented, with details of a very large scale integration (VLSI) design and characterization of critical circuits fabricated in complementary metal-oxide semiconductor (CMOS). The assignment problem requires that elements of two sets (e.g., resources and consumers) be associated with each other such as to minimize the total cost of the associations. Unlike previous neural implementations, association costs are applied locally to processing units (PUs, i.e., neurons), reducing connectivity to VLSI-compatible O(number of PUs). Also, each element in either set may be independently programmed to associate with one, several, or a range of elements of the other set. A novel method of “hysteretic annealing,” effected by gradually increasing positive feedback within each PU, was developed and compared in simulations to mean-field annealing implemented by increasing PU gain over time. The simulations (to size 64 × 64) consistently found optimal or near-optimal solutions, with settling times of about 150 microseconds, except for a few variable-gain annealing trials that exhibited oscillation.