Fault-tolerant and flexible interconnection of multiple processors

A study was undertaken to find out suitable forms of processor interconnection for large arrays of transputers that would provide complete flexibility for achieving dynamic reconfiguration without sacrificing the system's reliability. The feasibility of interconnecting links of 2 transputers through switch selectable paths has been established through experimentation, as reported elsewhere. Although the cross-bar interconnection network for multiprocessors exhibits better inherent reliability, it can easily be equaled and even bettered by employing redundant switches in the one-sided baseline system. This results in significant overall cost advantage and superior system availability, particularly during the initial period of system operation. Design techniques for implementing fault-tolerant multitransputer systems are outlined. The principles of achieving a specified degree of reliability in such systems over a required period of time are illustrated.