Predicting Transient Upset in Gate Arrays

Predicting Transient Upset in Gate Arrays

A simulation program for predicting dose rate upset has been adapted from the Power Analysis for Integrated Circuits program (PANIC). The program provides detailed analysis on the Vcc-Vss difference at any location within the array as well as the amount of photocurrent being collected, as a function...

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Veröffentlicht in:IEEE transactions on nuclear science 1987-12, Vol.34 (6), p.1426-1430
Hauptverfasser: Woodruff, Richard L., Nelson, Donald A., Scherr, Steven
Format: Artikel
Sprache:eng
Schlagworte:
Analytical models
Circuit analysis
Circuit simulation
Circuit testing
CMOS logic circuits
Current density
Frequency
Logic arrays
Power dissipation
Rails
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Beschreibung
Zusammenfassung:A simulation program for predicting dose rate upset has been adapted from the Power Analysis for Integrated Circuits program (PANIC). The program provides detailed analysis on the Vcc-Vss difference at any location within the array as well as the amount of photocurrent being collected, as a function of design. The simulation has been compared to experiment for a specific design and was found to correlate to within 20% at 5 volts.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.1987.4337492