Analysis and experimental verification of parasitic oscillations in paralleled power MOSFET's

An analysis of the small signal dynamic model of the power MOSFET is presented which predicts the existence of high-frequency parasitic oscillations when these devices are electrically paralleled. It is shown that the existence of these oscillations is a strong function of the small signal transfer admittance g sub(m) and the differential mode drain, gate, and source resistances. The sensitivity of the oscillations to these parameters is determined. Experimental data verifying the qualitative aspects of the analytical results is presented. It is concluded that the problem is potentially most severe for devices which are paralleled by the manufacture at the chip level. A practical solution to the problem is the introduction of differential mode gate resistance, either as lumped components, or by the use of polysilicon overlays.