Selective silicon epitaxial growth for device-isolation technology

Selective silicon epitaxial growth using the SiH 2 Cl 2/ HCl/ H 2 system under reduced pressure was accomplished in windows surrounded by a fine patterned insulator film on a silicon substrate. Selectivity, surface planarity, and facet formation were studied as a function of growth pressure, growth temperature, and HCl flow rate during selective epitaxial growth. Defects, which were mostly pairs of stacking faults, were observed along sidewalls. The defect density in the epi-layer decreased with both decreasing growth temperature and increasing HCl flow rate. Electrical properties of p-n junctions fabricated in the epi-layers were investigated. Polysilicon gate MOSFETs were successfully fabricated on the epitaxial silicon layers. It was revealed that the selective epitaxial growth isolation was effective to reduce latch-up susceptibility for CMOS circuits. It has been discovered that the selective epitaxial growth is applicable to fine and deep isolation and can realize submicron geometry isolation for VLSI.