Realtime implementation of the Viterbi decoding algorithm on a high-performance microprocessor

The complexity of the digital circuitry of the Viterbi decoder has prevented the algorithm from being fully exploited. One solution is to use a microprocessor to combat the complexity of the system. This paper presents a software implementation of the Viterbi algorithm on a high-performance microprocessor, for realtime decoding. The method implemented is based on forming a set of tables and using the internal structure of the processor for table manipulation rather than calculations. The paper gives a practical solution to the problem of memory management. The algorithm is reviewed mainly to define the necessary computational stages, with a detailed description of the software implementation of each stage. Also included is a comparison of the performance of the chosen processor with that of other processors, the results obtained showing a substantial improvement in performance over that of other microprocessor implementations published in the literature. This implementation would be suitable for low- and medium-speed data modems.