Application of a solution proximity annealing technique for fabrication of ion-implanted GaAs integrated circuits

A technique for capless annealing of ion-implanted GaAs, using an arsenic-saturated solution of Sn and Ga in close proximity to the wafer, has been applied to the fabrication of GaAs integrated circuits. The IC processing technology utilizes a self-aligned T-shaped refractory gate approach for the fabrication of both enhancement- and depletion-mode MESFET's. Using the solution proximity annealing technique, excellent threshold voltage uniformities (standard deviation = 26 mV) have been obtained for enhancement-mode devices using commercial substrates. This process technology has resulted in the fabrication of divide-by-16 circuits in both SDFL and DCFL logic implementations, as well as enhancement/depletion (E/D) ring oscillators (L g = 2 µm) with propagation delays as low as 45 ps/gate and concomitant power consumptions of 2 mW/gate. This technique can also be applied, by suitable choice of the solution constituents, to capless annealing of other III-V semiconductors such as InP and GaInAs.