Design of a Standard Floating-Point Chip
Some aspects of design of a VLSI floating-point chip, which provides the WE/spl registered/32100 microprocessor with math acceleration capabilities, are described. The chip is implemented in 1.75-/spl mu/m twin-tub CMOS II technology [2] and contains 140 000 transistors.
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Veröffentlicht in: | IEEE journal of solid-state circuits 1986-06, Vol.21 (3), p.396-399, Article 396 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | Some aspects of design of a VLSI floating-point chip, which provides the WE/spl registered/32100 microprocessor with math acceleration capabilities, are described. The chip is implemented in 1.75-/spl mu/m twin-tub CMOS II technology [2] and contains 140 000 transistors. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.1986.1052540 |