Damage-free mica/MoS2 interface for high-performance multilayer MoS2 field-effect transistors

For top-gated MoS2 field-effect transistors, damaging the MoS2 surface to the MoS2 channel are inevitable due to chemical bonding and/or high-energy metal atoms during the vacuum deposition of gate dielectric, thus leading to degradations of field-effect mobility ( FE) and subthreshold swing (SS). A top-gated MoS2 transistor is fabricated by directly transferring a 9 nm mica flake (as gate dielectric) onto the MoS2 surface without any chemical bonding, and exhibits excellent electrical properties with an on-off ratio of ∼108, a low threshold voltage of ∼0.2 V, a record FE of 134 cm2 V−1 s−1, a small SS of 72 mV dec−1 and a low interface-state density of 8.8 × 1011 cm−2 eV−1, without relying on electrode-contact engineered and/or phase-engineered MoS2. Although the equivalent oxide thickness of the mica dielectric is in the sub-5 nm regime, enhanced stability characterized by normalized threshold voltage shift (1.2 × 10−2 V MV−1 cm−1) has also been demonstrated for the transistor after a gate-bias stressing at 4.4 MV cm−1 for 103 s. All these improvements should be ascribed to a damage-free MoS2 channel achieved by a dry transfer of gate dielectric and a clean and smooth surface of the mica flake, which greatly decreases the charged-impurity and interface-roughness scatterings. The proposed transistor with low threshold voltage and high stability is highly desirable for low-power electronic applications.