Reduction of hardware expenses in control unit with code sharing

Reduction of hardware expenses in control unit with code sharing

A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocells, and existence of free outputs of embedded memory block in CPLD chips. An exampl...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Cybernetics and systems analysis 2013-05, Vol.49 (3), p.424-433
Hauptverfasser: Barkalov, O. O., Titarenko, L. A., Lavrik, A. S.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithms
Analysis
Artificial Intelligence
Chips (memory devices)
Control
Control algorithms
Control equipment
Cybernetics
Expenses
Hardware
Hardware industry
Logic
Mathematics
Mathematics and Statistics
Methods
Microprograms
Processor Architectures
Programmable logic controllers
Programmable logic devices
Software Engineering/Programming and Operating Systems
Studies
Systems analysis
Systems Theory
Variables
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocells, and existence of free outputs of embedded memory block in CPLD chips. An example of applying the method is given. It is shown that the method reduces hardware expenses to 30%.
ISSN:1060-0396
1573-8337
DOI:10.1007/s10559-013-9525-0