IO circuit design for 2.5D through‐silicon‐interposer interconnects

Summary This paper presents four topologies of voltage‐mode un‐terminated IO cells in 28‐nm CMOS for single‐ended rail‐to‐rail signaling over a passive interposer die in 2.5D configuration for >1Gbps data rates. The presented design explores the existing IO design‐space from a 2.5D viewpoint, optimizing existing topologies from area, speed, power and protection perspectives, with a higher degree of configurability in the form of pre‐emphasis and slew‐rate control. The transmitter (TX) embeds pre‐emphasis to enhance high‐frequency components of the signal for longer low‐pass natured channels. The TX also implements slew‐rate control to minimize reflections on shorter channels because of impedance discontinuities and also to minimize simultaneous switching noise. Level‐shifting capability embedded in the receiver (RX) enables multi‐technology interfacing where different dies are signaling at their core voltages (range: 0.7 V–1.8 V) instead of following a particular signaling standard. The measurement results of the transceivers, over a interposer of length of 3.5 mm, demonstrate ±5% duty‐cycle distortion with 700 μW at 500 MHz/0.8‐V‐signaling on the channel with jitter of 20 ps, ±10% duty‐cycle distortion with 1.8 mW at 1Gbps/0.9‐V signaling with jitter of 20 ps, ±10% duty‐cycle distortion with 2 mW at 2Gbps/0.7‐V signaling for 1‐V receiver core voltage with a jitter of 10 ps. Copyright © 2016 John Wiley & Sons, Ltd. Design details and measurement results of voltage‐mode unterminated IO cells in 28‐nm CMOS for single‐ended rail‐to‐rail signaling over a passive interposer die in 2.5D configuration for 1 Gbps data rates are presented. Four different transceiver configurations with respective merits and de‐merits demonstrate data rates from 1 Gbps to 4 Gbps for signaling voltages as low as 0.7 V and jitter as low as 10 psec over a 3.5‐mm long interposer.