Design of a constant fraction discriminator for the VFAT3 front-end ASIC of the CMS GEM detector

In this work the design of a constant fraction discriminator (CFD) to be used in the VFAT3 chip for the read-out of the triple-GEM detectors of the CMS experiment, is described. A prototype chip containing 8 CFDs was implemented using 130 nm CMOS technology and test results are shown.

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Veröffentlicht in:JINST 2016-01, Vol.11 (1), p.C01023-C01023
Hauptverfasser: Abbaneo, D., Abbas, M., Abbrescia, M., Abdelalim, A.A., Akl, M. Abi, Aboamer, O., Acosta, D., Ahmad, A., Ahmed, W., Aleksandrov, A., Aly, R., Altieri, P., Asawatangtrakuldee, C., Aspell, P., Assran, Y., Awan, I., Bally, S., Ban, Y., Banerjee, S., Barashko, V., Barria, P., Bencze, G., Beni, N., Benussi, L., Bhopatkar, V., Bianco, S., Bos, J., Bouhali, O., Braghieri, A., Braibant, S., Buontempo, S., Calabria, C., Caponero, M., Caputo, C., Cassese, F., Castaneda, A., Cauwenbergh, S., Cavallo, F.R., Celik, A., Choi, M., Choi, S., Christiansen, J., Cimmino, A., Colafranceschi, S., Colaleo, A., Garcia, A. Conde, Czellar, S., Dabrowski, M. M., Lentdecker, G. De, Oliveira, R. De, de Robertis, G., Dildick, S., Dorney, B., Elmetenawee, W., Endroczi, G., Errico, F., Fenyvesi, A., Ferry, S., Furic, I., Giacomelli, P., Gilmore, J., Golovtsov, V., Guiducci, L., Guilloux, F., Gutierrez, A., Hadjiiska, R.M., Hassan, A., Hauser, J., Hoepfner, K., Hohlmann, M., Hoorani, H., Iaydjiev, P., Jeng, Y. G., Kamon, T., Karchin, P., Korytov, A., Krutelyov, S., Kumar, A., Kim, H., Lee, J., Lenzi, T., Litov, L., Loddo, F., Madorsky, A., Maerschalk, T., Maggi, M., Magnani, A., Mal, P.K., Mandal, K., Marchioro, A., Marinov, A., Masod, R., Majumdar, N., Merlin, J.A., Mitselmakher, G., Mohanty, A.K., Mohamed, S., Mohapatra, A., Molnar, J., Muhammad, S.
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Sprache:eng
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Zusammenfassung:In this work the design of a constant fraction discriminator (CFD) to be used in the VFAT3 chip for the read-out of the triple-GEM detectors of the CMS experiment, is described. A prototype chip containing 8 CFDs was implemented using 130 nm CMOS technology and test results are shown.
ISSN:1748-0221
1748-0221
DOI:10.1088/1748-0221/11/01/C01023