A single shot TDC with 4.8 ps resolution in 40 nm CMOS for high energy physics applications

A robust TDC with 4.8 ps bin width has been designed for harsh environments and high energy physics applications. The circuit uses resistive interpolation DLL with a novel dual phase detector architecture. This architecture improves startup- and recovery speed from single event strikes without control voltage ripple trade-off and requires no off-line calibrations. A 0.43 LSB DNL has been measured at a power consumption of 4.2 mW with an extended frequency range from 0.8 GHz to 2.4 GHz. The TDC has been processed in 40 nm CMOS technology.