Visualization of Gate-Bias-Induced Carrier Redistribution in SiC Power DIMOSFET Using Scanning Nonlinear Dielectric Microscopy
Carrier profiling in the cross section of a gate-biased silicon carbide power double-implanted MOSFET is demonstrated with a newly developed measurement system that utilizes super-higher-order scanning nonlinear dielectric microscopy. Two techniques that have features that complement each other were...
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Veröffentlicht in: | IEEE transactions on electron devices 2016-08, Vol.63 (8), p.3165-3170 |
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Hauptverfasser: | , |
Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | Carrier profiling in the cross section of a gate-biased silicon carbide power double-implanted MOSFET is demonstrated with a newly developed measurement system that utilizes super-higher-order scanning nonlinear dielectric microscopy. Two techniques that have features that complement each other were proposed and demonstrated. In all measurements, the tip-sample voltage difference was cancelled during gate-source voltage (V GS ) application. Variation in the V GS -dependent carrier distribution was reasonably determined using both of the proposed techniques. |
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ISSN: | 0018-9383 1557-9646 |
DOI: | 10.1109/TED.2016.2571780 |