Vertical Slit FET at 7-nm Node and Beyond

Vertical Slit FET at 7-nm Node and Beyond

This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication har...

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Veröffentlicht in:IEEE transactions on electron devices 2016-08, Vol.63 (8), p.3327-3334
Hauptverfasser: Ping-Lin Yang, Hook, Terence B., Oldiges, Philip J., Doris, Bruce B.
Format: Artikel
Sprache:eng
Schlagworte:
Atomic measurements
Channels
Circuit design
CMOS
Devices
FinFET
FinFETs
Gates (circuits)
Hardware
Layout
Logic gates
Metals
Slits
SOI
TCAD
Terminals
vertical slit FET (VeSFET)
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Beschreibung
Zusammenfassung:This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication hardware. The second gate provides the capability of transistor behavior adjustment and the potential for advanced circuit designs. The results show that VeSFET can provide high I eff to I off ratio, low gate capacitance, high ΔV t /V g2s , and competitive drive capability with respect to a reference FinFET of comparable dimensions.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2016.2577629